Charles Lee Powell Chair in Engineering in the Ming Hsieh Department of Electrical and Computer Engineering and Professor of Computer Science at the University of Southern California
- November 28, 2022
- 2:00 PM
- CASE 241 & Zoom
Viktor K. Prasanna is Charles Lee Powell Chair in Engineering in the Ming Hsieh Department of Electrical and Computer Engineering and Professor of Computer Science at the University of Southern California. He is the director of the Center for Energy Informatics at USC and leads the FPGA and Data Science Labs. His research interests include parallel and distributed computing, accelerator design, reconfigurable architectures and algorithms and high performance computing. He serves as the Editor-in-Chief of the Journal of Parallel and Distributed Computing. Prasanna was the founding Chair of the IEEE Computer Society Technical Committee on Parallel Processing. He is the Steering Chair of the IEEE International Parallel and Distributed Processing Symposium. He is a Fellow of the IEEE, the ACM and the American Association for Advancement of Science (AAAS). He is a recipient of 2009 Outstanding Engineering Alumnus Award from the Pennsylvania State University and a 2019 Distinguished Alumnus Award from the Indian Institute of Science. He received the 2015 W. Wallace McDowell award from the IEEE Computer Society for his contributions to reconfigurable computing. He is a member of Academia Europaea.
With recent dramatic advances in Field Programmable Gate Arrays (FPGAs), these devices are being used along with multi-core and novel memory technologies to realize advanced platforms to accelerate complex applications in the Cloud. We will review advances in reconfigurable computing over the past 25 years leading up to accelerators for data science. We will illustrate FPGA-based parallel architectures and algorithms for a variety of data analytics kernels in streaming graph processing and graph machine learning. While demonstrating algorithm-architecture co-design methodology to realize high performance accelerators for graphs and machine learning, we demonstrate the role of modeling and algorithmic optimizations to develop highly efficient Intellectual Property (IP) cores for FPGAs. We show improved performance for two broad classes of graph analytics: iterative graph algorithms with variable workload (e. g., graph traversal, shortest paths, etc.) and machine learning on graphs (e. g., graph embedding). For variable workload iterative graph algorithms, we illustrate dynamic algorithm adaptation to exploit heterogeneity in the architecture. We conclude by identifying opportunities and challenges in exploiting emerging heterogeneous architectures composed of multi-core processors, FPGAs, GPUs and coherent memory.